1. Field of the Invention
This invention relates to integrated circuits, and particularly to metal oxide semiconductor large scale integrated circuit (MOS/LSI) devices having N-channel or P-channel MOS field effect transistors, such as are commonly used in hand calculators, home and office computers, automotive and industrial control systems and other commercial products. MOS/LSI devices use numerous circuit designs to achieve specific functions. One of the circuit designs used in MOS/LSI devices is a tri-state driver circuit, i.e., a circuit which has a first or logic one state, a second or logic zero state and a third or float state operation as output states, and which interfaces with and functions to drive output loads, external or internal to the MOS/LSI device, in response to low power signal sources within the MOS/LSI device. The circuit also functions to disconnect the tri-state driver circuit output from the output load when commanded to begin float state operation, in response to a complement float command.
The advantage that a tri-state driver circuit has over a two state driver circuit,(no float state) is that when the former circuit is commanded to the third or float state, no voltage is applied to the output load. The output of the circuit appears to be disconnected from the output load. The conductive paths to the output load are interrupted. The outputs of more than one tri-state driver circuit can therefor be connected to the same output load.
The principal advantage of this tri-state driver circuit is that it substantially reduces the internal power consumption of the circuit with no sacrifice in speed. This makes it possible to expand the number of circuits available in a given MOS/LSI device where the available power is limited.
2. Description of the Prior Art
Presently known tri-state driver circuits are usually comprised of: NOR gates; buffer switches for pulling up the output of the NOR gates; and an output driver stage that applies voltage to the output load. Such tri-state driver circuits dissipate the greatest amount of system power when in the float state, because the NOR circuits used in these tri-state driver circuits rely on a buffer switch to provide power to the output of the NOR gate. The buffer switches typically used in MOS/LSI devices employing a single voltage source can be made highly conductive or slightly conductive, but they cannot be cut off completely. With the output of the NOR circuit low, the respective buffer switch must drop the power supply voltage (VDD minus VSS), the power dissipated in the buffer switch remaining undesirably high because the switch continues to provide a small bias current although turned off.
Patents in the field of the invention include: U.S. Pat. No. 4,194,131, "TRISTATE LOGIC BUFFER CIRCUIT WITH ENHANCED DYNAMIC RESPONSE" and U.S. Pat. No. 4,194,132, "TRISTATE LOGIC BUFFER CIRCUIT WITH REDUCED POWER CONSUMPTION" both issued on Mar. 18, 1980 to Dale A. Marazek. Both of these patents differ substantially in topology from the present invention and neither teaches a method or means for reducing the power consumed in a tri-state driver circuit using MOS FET transistors.
Other Patents of interest include: U.S. Pat. No. 4,280,065, "TRI-STATE TYPE DRIVER CIRCUIT" issued on July 21, 1981 to Osamu Minato; U.S. Pat. No. 4,037,114, "TRI-STATE LOGIC CIRCUIT" issued on July 19, 1977 to Roger Green Stewart; and U.S. Pat. No. 3,906,255, "MOS CURRENT LIMITING OUTPUT CIRCUIT" issued on Sept. 16, 1975 to William David Mensch, Jr.
None of the above references require a two phase clock signal input such as is used by the invention tri-state driver circuit. None of the above referenced circuits employ a voltage dependent capacitor means operating in cooperation with a first and second switching means and a current limiting means as defined in FIG. 2 of the invention tri-state driver circuit. In addition, the referenced patents do not contemplate a two phase clock driven power switch for enabling an array of tri-state driver circuits means with an enable signal approximating a single supply voltage, VDD, during a particular clock phase interval.
Another reference of interest is U.S. patent application Ser. No. 174,089 filed July 31, 1980 and having as inventor Gary L. Heimbigner, and titled "REDUCED POWER TRISTATE DRIVER CIRCUIT". The Heimbigner circuit does not utilize a two phase clock signal nor does it incorporate a voltage dependent capacitive means operating in cooperation with a first and second switching means and a current limiting means to generate an enable signal. The Heimbigner reference requires complementary float signal inputs and does not envision a single float signal being used to control a power switch means to generate an enable signal for controlling an array of tri-state driver circuit means.